How we design, generate, and prove verified FPGA IP, written for the engineers who evaluate it. Every number in these pieces is a measured result.
A generated decoder, handed to an AI to shrink its FPGA footprint. AI folded the logic to a third, diagnosed that the lost clock was a micro-architecture problem not a folding one, swapped in a rotating read to recover 160 MHz, backed out of a measured dead end, and proved every change bit-exact.
A complete 802.11a receiver went from a MATLAB reference design to bit-exact FPGA hardware no one wrote by hand, and recovered a MATLAB-generated waveform with zero bit errors. How every layer was checked against the standard.
A 5G LDPC decoder, generated as RTL from a Python algorithm, optimized from 221 to 463 MHz, past a paid commercial IP on the same FPGA. The hard part was the data dependency between layers, not where to add a register.
One parameterized flow generates, timing-closes, and bit-exact verifies twenty 5G LDPC decoder configurations. Tuning one design is a special case; automating the whole batch, and proving every one, is a method.