Algorithm to deployed system

Algorithms, running
on real hardware.

AlgoSilicon takes an algorithm from a Python or MATLAB reference all the way onto working silicon, across the host CPU, the embedded ARM, and the FPGA fabric of real radios and edge platforms. An AI-driven automation flow generates the hardware, bit-exact and timing-closed, verified at every layer. Verified FPGA IP cores are one of the things we ship. Every performance number is a measured tool result.

See it deployed Explore IP cores
8 / 8
802.11a Wi-Fi data rates recovered bit-exact over the air, on an ADALM-Pluto SDR MEASURED
463 MHz
5G LDPC decoder, place-and-route closed MEASURED
0 LSB
RTL vs golden-model mismatch across validation suites MEASURED
19/20
generated configs match or beat a commercial IP's clock MEASURED
01 / HOW IT WORKS

Prototype, verify, deploy

We close the distance between an algorithm and a working product on real hardware. The same flow serves researchers proving an idea, developers building a prototype, and engineers shipping an edge product, across wireless and 5G, satellite and space, software radio, and edge AI.

Prototype

algorithm to architecture

Start from a Python or MATLAB reference. An AI-driven flow restates it as a golden model, scores candidate hardware architectures on throughput, latency, and resources, and picks the one that fits your device.

Verify

bit-exact, every layer

The generated RTL is checked against a cycle-accurate model and the golden reference to zero least-significant bits, across the hardest realistic inputs, then placed and routed on your part with the Vivado timing and utilization reports as the record.

Deploy

host CPU + ARM + FPGA

When a design outgrows one chip, we split it across the tiers of the platform: the rate-critical path in the FPGA fabric, data movement on the embedded ARM, the heavy back end on the host CPU. Demonstrated on an ADALM-Pluto radio over the air; we target the same method on RFSoC, USRP, and NPU/GPU accelerators.

02 / PRODUCTS

IP cores, generated and verified

Each core family is produced by a parameterized generator: change the code parameters and a new, bit-exact decoder or pipeline is emitted and re-verified automatically. These are the verified building blocks we deploy into real systems. You license proven silicon, and the ability to re-target it in days.

Wireless PHY

802.11a Wi-Fi RX · OFDM

A complete 802.11a Wi-Fi receiver physical layer: synchronization, OFDM demodulation, equalization, soft demapping, and Viterbi decoding. A MATLAB-generated standard waveform is recovered bit-for-bit on a fingernail-sized FPGA.

End-to-end recovery0 errors MEASURED
Receive clock (Zynq-7010)162.7 MHz MEASURED
Line rate54 Mbps MEASURED
Wireless PHY family

Cellular PHY

5G NR SSB RX · cell search

A 5G NR cell-search receiver: primary-synchronization detection, SSB extraction, a 256-point OFDM demodulation, and the full broadcast decode to the Master Information Block. Three real over-the-air cells are read to a consistent broadcast message.

Real cells decoded3 / 3 CRC clean MEASURED
Detector vs earlier HLS38% fewer LUTs MEASURED
Receive clock (KV260)256 MHz MEASURED
Cellular PHY family

LDPC Decoders

5G NR · IEEE 802.11n · CCSDS

Layered and folded QC-LDPC decoders for 3GPP 5G NR (BG1/BG2, all lifting sizes), Wi-Fi, and CCSDS AR4JA deep-space links. Syndrome-based early termination, zero DSP usage, single-CNU area class.

Clock (5G NR, xcku13p)463 MHz MEASURED
Throughput (early-stop)>1 Gbps MEASURED
DSP blocks0
LDPC family

Viterbi Decoder

convolutional FEC · Wi-Fi · DVB · LTE · satellite

A soft-decision Viterbi decoder for rate-1/2 convolutional codes, K=7 and K=9. One decoded bit per clock, zero DSP, and open RTL verified bit-for-bit against the reference decoder, where the common commercial core ships encrypted.

Clock (K=7, UltraScale+)527 MHz MEASURED
Throughput527 Mbps MEASURED
DSP blocks0
Viterbi decoder

DSP Pipelines

FFT · FIR · CIC · NCO/DDS

Streaming FFT engines (1k–8k points) and a 58-variant FIR filter family: symmetric, systolic, multi-channel TDM, polyphase resamplers, digital up/down-conversion chains. One sample per clock, every clock.

FFT clock (1k–8k)404–446 MHz MEASURED
FIR clock (peak)485 MHz MEASURED
Initiation intervalII = 1
DSP family

Trading Systems

Limit order book · market data

A hardware limit-order-book builder processing one exchange message per clock cycle, verified bit-exact against real NASDAQ market-data replay. Hierarchical symbol caching scales to full-market coverage.

Pipeline clock361 MHz MEASURED
Hot-path latency11 cycles MEASURED
Wire-to-wire130 ns TARGET
Trading family

Quantum LDPC

QEC decoding · in development

Relay belief-propagation decoder for quantum error correction on bivariate-bicycle codes (the IBM "gross" code). FPGA-pipelined BP iteration already clocking past the published reference implementation.

BP iteration clock118 MHz MEASURED
Published reference83 MHz
StatusIN DEVELOPMENT
qLDPC program
03 / SERVICES

Design and deployment services

The same automation that builds our IP works on your algorithm. We take a Python or MATLAB reference to verified, timing-closed RTL, rescue an existing design that will not close timing, and take a validated design onto real hardware.

Algorithm to RTL

Your signal-processing or decision algorithm, delivered as bit-exact synthesizable RTL with a full verification suite. Typical delivery 2–8 weeks.

How it works

Timing-closure rescue

An automated closure flow that classifies every failing path and applies the right structural fix. Case study: a 5G LDPC decoder taken from 221 MHz to 463 MHz on the same device. MEASURED

Closure flow

IP customization

New code rates, block sizes, channel counts, or target devices for any core in our catalog, regenerated and re-verified in about a week, not a redesign.

Variants

Deploy on real hardware

A validated design taken onto a real SDR or heterogeneous platform: partitioned across FPGA fabric, embedded ARM, and host CPU, brought up rung by rung, bit-exact on every tier. Proven on an ADALM-Pluto Wi-Fi link, over the air.

Deployment
04 / METHODOLOGY

Three layers, zero hand-waving

Every product passes a strict three-layer equivalence chain: a golden mathematical model validated against the published standard, a cycle-accurate Python model validated against the golden model, and RTL validated bit-exact against the cycle model, to zero least-significant-bit tolerance.

Performance claims follow the same discipline. If a number on this site is not a real synthesis, place-and-route, or simulation result, it is labeled a target.

Inside the methodology
Three-layer modeling: golden math model, cycle-accurate model, Verilog RTL
The measured-numbers promise

Every figure on this site traces to a tool report: a Vivado timing summary, a utilization report, or a cycle-accurate simulation log. Numbers we have not yet measured are explicitly badged as targets. Ask us for the evidence behind any claim and we will show you the report.

Request an evaluation