Streaming FFT engines and a deep FIR filter catalog for software-defined radio, radar, and instrumentation front ends. Every pipeline accepts one sample per clock, every clock - and is verified bit-exact against a golden floating-point reference.
Single-delay-feedback architectures in radix-2 and radix-2², measured on AMD Zynq UltraScale+ RFSoC (xczu28dr). Both radix variants ship - choose DSP-lean or logic-lean per system budget.
| Configuration | Clock MEASURED | Throughput | LUT | DSP | BRAM36 |
|---|---|---|---|---|---|
| 1024-point, radix-2² | 444.6 MHz | 444.6 Msamp/s | 1,021 | 20 | 7 |
| 1024-point, radix-2 | 433.1 MHz | 433.1 Msamp/s | 934 | 40 | 8 |
| 4096-point, radix-2² | 446.0 MHz | 446.0 Msamp/s | 1,322 | 24 | 21 |
| 8192-point, radix-2 | 403.6 MHz | 403.6 Msamp/s | 1,336 | 52 | 37 |
All four configurations: initiation interval 1 (one sample per clock, measured, not declared), RTL bit-exact 0 LSB versus the cycle-accurate model, and within tolerance of the floating-point golden reference across impulse, DC, sine, and random stimulus. Vivado place-and-route on xczu28dr, 400 MHz target.
Fifty-eight verified variants across eleven topology classes - because a filter is never just "a filter". Pick the topology that matches your sample rate, channel count, and resource budget; we regenerate the exact configuration you need.
Coefficient symmetry folded into DSP pre-adders - half the multipliers of a direct form. Systolic DSP-cascade variants for the highest clocks.
Time-division multiplexed banks (2/4/8 channels), parallel super-sample-rate paths, polyphase rational resamplers, and half-band decimators.
CIC decimators/interpolators (multiplier-free), NCO/DDS tone generation, I/Q mixers, and complete digital up/down-conversion chains assembled from verified blocks.