Layered and folded quasi-cyclic LDPC decoders for 3GPP 5G NR, IEEE 802.11n, and CCSDS AR4JA, generated from one parameterized architecture, verified bit-exact at every configuration, and timing-closed against a commercial reference IP on the same silicon.
Our flagship configuration (base graph 2, lifting size 384, K = 3840) was placed and routed on the same AMD Kintex UltraScale+ device class the commercial reference IP publishes its numbers on. All figures below are from Vivado Design Timing Summary and utilization reports.
5G NR specifies two base graphs and 51 lifting sizes. Because our decoder is emitted by a parameterized generator, we regenerated and re-implemented 20 distinct configurations end to end:
| Result across 20 generated configurations | Value | Provenance |
|---|---|---|
| Configurations matching or beating the commercial IP's 459 MHz clock | 19 / 20 | Vivado P&R, per config MEASURED |
| Median clock ratio vs commercial IP | 1.03× | Vivado Design Timing Summary MEASURED |
| Fastest configuration | 566 MHz | Vivado Design Timing Summary MEASURED |
| Slowest configuration (densest base matrix, routing congestion) | 408 MHz | Reported as-is. We publish misses too MEASURED |
Fair-comparison note: the commercial IP is a runtime-flexible multi-standard core; our cores are per-configuration specialized netlists, which is precisely what the generator makes economical. Throughput depends on iteration count: figures with early termination are stated at the operating SNR; fixed-iteration apples-to-apples figures are available in the datasheet on request.
Deep-space links get one chance at a frame: there is no retransmission across an interplanetary distance, so the decoder has to be right the first time and it has to keep running. The build below is our evaluation twin: it mirrors the MathWorks CCSDS LDPC Decoder block module by module in scalar mode, which makes it directly comparable against a known reference and makes its correctness auditable line by line. It trades throughput for that comparability, so it is slower than the folded configuration we ship for rate-critical links. It is also the one we took all the way to a board, so it is the one whose numbers we publish.
Measured by interface lockstep at a fixed 8 iterations: the first output bit lands at an exactly predicted cycle for every configuration. These are the evaluation twin's figures, in scalar mode. The folded product configuration processes several lanes per cycle and is correspondingly faster; ask us for figures on your target part rather than scaling these.
| Configuration | Transmitted bits | Cycles / iteration | Frame latency (cycles) | Cycles / info bit |
|---|---|---|---|---|
| k = 1024, rate 1/2 | 2048 | 252 | 5,097 | 4.98 |
| k = 1024, rate 2/3 | 1536 | 316 | 5,097 | 4.98 |
| k = 1024, rate 4/5 | 1280 | 444 | 5,865 | 5.73 |
| k = 4096, rate 1/2 | 8192 | 1240 | 22,217 | 5.42 |
| k = 4096, rate 2/3 | 6144 | 844 | 17,001 | 4.15 |
| k = 4096, rate 4/5 | 5120 | 444 | 12,777 | 3.12 |
| k = 16384, rate 1/2 | 32768 | 4960 | 88,841 | 5.42 |
| k = 16384, rate 2/3 | 24576 | 3376 | 67,977 | 4.15 |
| k = 16384, rate 4/5 | 20480 | 2584 | 57,545 | 3.51 |
Fixed 8 iterations, no early termination, so these are worst-case figures rather than best-case ones. Early termination on the syndrome check is available and reduces the average iteration count at operating SNR. This twin closed timing at its 208.3 MHz constraint on a ZCU102 (xczu9eg) with WNS +0.091 ns post-route; we are not publishing a clock for the RFSoC part, because the builds we have on that part do not meet that constraint. Device clock and resource figures for the folded product configuration on your target part are produced per configuration on request. We publish only numbers we have measured, on the part we measured them on.
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Real recorded data from the board: every frame, every configuration, the bit-error comparison and the BER waterfall. No hardware needed.
Layered normalized-min-sum decoding with syndrome early termination. Golden model cross-validated bit-exact against MATLAB 5G Toolbox encode/decode across 40 trials and 7 configurations.
All nine AR4JA code points of CCSDS 131.0-B-3: block lengths 1024, 4096 and 16384 information bits, each at rate 1/2, 2/3 and 4/5. The folded configuration trades parallelism against area for rate-critical or power-constrained platforms; a scalar evaluation twin of the MathWorks reference block is the build we verified bit-exact on real silicon, across all nine.
Continuously streaming decoder accepting one codeword after another with no inter-frame gap. The architectural template behind the whole family.
Need a different standard, rate, or block size? New configurations are generated and re-verified in days: see IP customization.
Walk through the full 5G NR decoder design (architecture, verification chain, and the timing-closure campaign) in our interactive engineering report.