Layered and folded quasi-cyclic LDPC decoders for 3GPP 5G NR, IEEE 802.11n, and CCSDS AR4JA - generated from one parameterized architecture, verified bit-exact at every configuration, and timing-closed against a commercial reference IP on the same silicon.
Our flagship configuration (base graph 2, lifting size 384, K = 3840) was placed and routed on the same AMD Kintex UltraScale+ device class the commercial reference IP publishes its numbers on. All figures below are from Vivado Design Timing Summary and utilization reports.
5G NR specifies two base graphs and 51 lifting sizes. Because our decoder is emitted by a parameterized generator, we regenerated and re-implemented 20 distinct configurations end to end:
| Result across 20 generated configurations | Value | Provenance |
|---|---|---|
| Configurations matching or beating the commercial IP's 459 MHz clock | 19 / 20 | Vivado P&R, per config MEASURED |
| Median clock ratio vs commercial IP | 1.03× | Vivado Design Timing Summary MEASURED |
| Fastest configuration | 566 MHz | Vivado Design Timing Summary MEASURED |
| Slowest configuration (densest base matrix, routing congestion) | 408 MHz | Reported as-is - we publish misses too MEASURED |
Fair-comparison note: the commercial IP is a runtime-flexible multi-standard core; our cores are per-configuration specialized netlists, which is precisely what the generator makes economical. Throughput depends on iteration count: figures with early termination are stated at the operating SNR; fixed-iteration apples-to-apples figures are available in the datasheet on request.
Layered normalized-min-sum decoding with syndrome early termination. Golden model cross-validated bit-exact against MATLAB 5G Toolbox encode/decode across 40 trials and 7 configurations.
All nine AR4JA code points (three block lengths, three rates) verified through the full flow. Configurable parallelism trades throughput against area for power-constrained space platforms.
Continuously streaming decoder accepting one codeword after another with no inter-frame gap. The architectural template behind the whole family.
Need a different standard, rate, or block size? New configurations are generated and re-verified in days - see IP customization.
Walk through the full 5G NR decoder design - architecture, verification chain, and the timing-closure campaign - in our interactive engineering report.