REPLAY · RECORDED SILICON CAPTUREZynq UltraScale+ RFSoC · overlay build 02471f0a8da5 · evaluation twin of the MathWorks reference block, scalar mode
1 / 675
0
frames through silicon
0
bits compared vs golden
0
bit mismatches
0 / 9
configurations verified
116 s
duration of the capture
5.8
frames / s during the capture
Per-config verdict · simulation vs silicon
simulation: 775 of 775 frames byte-exact against the golden model, all nine
configurations. silicon: replayed from the recorded on-board capture below.
BER waterfall · golden fixed-point vs MATLAB double
Check-node state churn (debug trace)
Decode event log
Every frame replayed here was decoded by the FPGA fabric on a real board and compared bit by bit
against the golden model on the host. The capture ran 675 frames across nine runtime
configurations (information block k of 1024, 4096 or 16384 bits, each at code rate 1/2, 2/3 and
4/5) with zero mismatches. The design under test is our evaluation twin of the MathWorks CCSDS LDPC
Decoder block, mirrored module by module in scalar mode for comparability against a known reference;
it is not the folded, higher-throughput configuration. Nothing is simulated in your browser and no
hardware is attached: the page is replaying recorded results, and the scrub bar moves through the
capture frame by frame.