A receiver that recovers the standard, bit for bit
The receiver was driven with waveforms produced by the MATLAB WLAN Toolbox, passed through a 12-bit ADC model, and decoded by the fixed-point hardware. Every figure below is a measured tool result: a Vivado place-and-route timing summary, a utilization report, or a bit-level cocotb cross-validation.
Characterized, then deployed three ways
The full receiver PHY is characterized as a complete place-and-route on a Zynq-7010, and separately on a Zynq UltraScale+ RFSoC for clock headroom. On the ADALM-Pluto itself the full PHY does not fit alongside the radio's own interface logic, so the on-radio deployment is split across three tiers: the synchronization front-end in the FPGA, the rest on the host, and validated over the air. Every figure is a real measured result.
| Result | Value | Provenance |
|---|---|---|
| Receive clock, full PHY (Zynq-7010 place-and-route) | 162.7 MHz | Vivado P&R, dual-clock MEASURED |
| Receive clock, Zynq UltraScale+ RFSoC (characterization) | 309.6 MHz | Vivado Design Timing Summary MEASURED |
| Logic, full PHY (Zynq-7010 place-and-route) | 8,514 LUT / 8,233 FF | Vivado utilization MEASURED |
| Delivered image over the air, all 8 modes | 100% bit-exact | 831 / 832 raw per packet, a channel hit MEASURED |
| Continuous decode on the Pluto, 90 s run | 1390 / 1390 | every packet, no reset MEASURED |
| End-to-end recovery, MATLAB waveform to fixed-point receiver | 0 errors / 38,400 bits | bit-level cross-validation MEASURED |
The full PHY (about 8,500 logic cells) plus the radio's interface logic (about another 8,500) exceed the 17,600 on the Pluto, so the on-radio deployment keeps the rate-critical synchronization front-end in the FPGA and runs the heavier back end on the host, bridged by DMA then USB. It runs continuously: it consumes an unbroken stream of baseband samples, finds each packet on its own, and decodes one after another with no reset, recovering the transmitted bits exactly across all eight data rates.
