A hardware limit-order-book builder that consumes one exchange message every clock cycle, with no stalls and no queue build-up at market open. Verified bit-exact, message by message, against replay of real NASDAQ market data.
A seven-stage pipeline maintains price-level depth for adds, executions, cancels, deletes and trading-state events, sustaining one message per cycle at full clock rate on AMD Alveo-class devices.
Functional correctness is proven the only way that matters for trading infrastructure: against recorded reality.
| Verification evidence | Result |
|---|---|
| Synthetic stress stream (20,000 operations, all message types) | 25,962 cycles bit-exact MEASURED |
| Real NASDAQ replay (LOBSTER, AMZN full trading day extract) | bit-exact every cycle MEASURED |
| Golden reference | Cross-validated line-by-line against an actively maintained open-source backtesting engine |
| Resource footprint (top level) | 610 LUT / 1,726 FF / 16 BRAM36 MEASURED |
The multi-symbol extension adds a hierarchical symbol cache: hot symbols in on-chip BRAM, warm in URAM, the full universe in HBM, so a single card tracks the entire equity market while keeping hot-symbol latency unchanged. Golden model complete and validated; hardware integration in progress. IN DEVELOPMENT
Market-open bursts overwhelm designs that average their throughput. An II=1 pipeline has no average. Worst case equals best case, so your strategy never reads a stale book at exactly the moment it matters most.
Signals derived from book state (imbalance, microprice, queue position) drop into the same verified pipeline as additional stages. We build these as design-service engagements under NDA.
Design services