Every wireless generation trades complexity for coding gain: a stronger error-correcting code lets the same radio close the link at a lower signal-to-noise ratio, or reach the same range at lower power. LDPC replaced the convolutional codes of earlier standards for exactly that reason. The question a datasheet rarely answers honestly is how much of that gain survives a real fixed-point decoder on real silicon. We put one on a board and measured it.
A complete coded link runs on a custom RFSoC board. The transmitter builds standard-compliant frames, the signal goes out through a data converter, around an SMA cable loopback, back in through the receive converter, and an LDPC decoder in the fabric recovers the payload. The whole radio link is one cable, so the experiment is honest: if a frame comes back wrong, the fault is ours.
A link that stays up
Before measuring anything, the link has to be stable. Running continuously for two hours over the cable loopback, under a schedule that keeps switching the coding and the modulation to exercise the recovery paths, the decoder held its output error-free across 236 measured samples, with zero anomalies, zero re-arms, every frame completing in full, at about 23 Mbps of sustained decoded goodput. MEASURED
The coding gain, measured
To measure coding gain you compare two codes on the same channel. On the identical link geometry, the same modulation and the same frame length, we swept the signal-to-noise ratio and found where each code's frame-error rate crosses one half. The LDPC decoder reaches that point at 12.6 dB; the legacy convolutional code needs 13.8 dB. The difference, 1.14 dB, is the coding gain the LDPC decoder delivers on silicon, in fixed point, end to end. MEASURED
This is the conservative figure. It was measured at the shortest frame, where a block code has the least room to work. Longer frames give the decoder a longer codeword to exploit, and the gain grows from here. The short-frame number is a floor.
Every mode, every boot
A coding gain measured once could be luck. The decoder was run across the standard's modulation-and-coding schemes, on four separate cold boots of the board, each run paired with a deliberately corrupted control that had to fail. Every in-scope configuration decoded, up to 599 of 600 frames per run, and every control failed as required. MEASURED The deployed decoder targets one codeword length; configurations that use a different length are stated as out of scope rather than quietly skipped.
Closing timing on the part
The decoder closes timing on the RFSoC part with margin. Across a sweep of placement strategies the median clock is 161.5 MHz, against a 160 MHz target. MEASURED
What it means
The path from a coded-link algorithm to a deployed, measured result on real silicon is now short enough to run as an ordinary experiment. Build the link, put it on the board, and read the coding gain off the hardware. The number that comes back is measured, 1.14 dB and rising with frame length, on the same board that ran error-free for two hours.
The decoder family behind this link is described on the LDPC decoders page.